This disclosure relates to integrated circuit devices. More specifically, to designing interconnect wiring structures in semiconductor devices.
Integrated circuits are fashioned by creating a plurality of devices in a substrate which are interconnected by multiple layers of interconnections. The process starts with a chip designer constructing the layout of a new chip design with the use of an electronic design automation (EDA) tool. One of the tasks automated by such tools is the wire routing, or simply routing, of the wiring between devices within the available space allocated to the metal layers and the vias which interconnect the metal layers. Speed in the design process is an important criterion for an EDA system. Design tools which provide rapid, accurate results, especially for large complex designs are valuable so that designers can make decisions quickly on design tradeoffs without needing to wait for days to even weeks to obtain accurate results from the system.
It is typical that the routing process used by an EDA tool contains a global routing phase and a detail routing phase. Global routing in modern circuit design is used to establish an approximate route of the wiring between devices. Detailed routing will follow the global routing and route the actual wires to the devices. The global routing is simpler than the detail routing problem, because it does not see many of the small details that detail routing has to solve. Therefore, it has several advantages including that global routing is much faster than detail routing. Further, global routing can be designed in such a way that its results are “provably optimal”, in other words, it has some quality guarantees. Global routing is used as guidance for detail routing, e.g., used for wire resource allocation and fast estimation purposes. It is desirable that the global routing be as accurate as possible to minimize computations needed in the rip-up and reroute step.
The capacity model used in the typical state of the art router uses a simplified measure of the wiring capacities between tiles in the same metal layer. When modelling integrated circuits for future semiconductor processing technologies, such as the Self Aligned Double Patterning (SADP) manufacturing process, the simple capacity model has major flaws.
The present disclosure presents an advanced electronic design mechanism to alleviate these problems.